The invention relates to a memory cell configuration for the nonvolatile storage of data. For the nonvolatile storage of data, memory cell configurations have been proposed in which each memory cell has at least one ferroelectric transistor (see European Patent EP 0 566 585 B1, corresponding to U.S. Pat. No. 5,471,417 to Krautschneider). The term ferroelectric transistor in such a case refers to a transistor having two source/drain regions, a channel region, and a gate electrode. A ferroelectric layer, that is to say, a layer made of ferroelectric material, is provided between the gate electrode and the channel region. The conductivity of the transistor is dependent on the polarization state of the layer made of ferroelectric material. Such ferroelectric transistors are being investigated with regard to nonvolatile memories. In such a case, two different logic values of a digital information item are assigned two different polarization states of the layer made of ferroelectric material.
In the memory cell configuration disclosed in European Patent EP 0 566 585 B1, it is proposed to apply a voltage individually for the different memory cells below the ferroelectric layer at the substrate, in order, when writing information to one memory cell, to avoid altering the information in other, non-selected memory cells. To that end, there is provided below the active transistor region a doped layer, which is insulated from the general substrate by pn junctions and is insulated from adjacent memory cells by insulation regions, which represents an individual substrate for the individual ferroelectric transistor.
Another memory cell configuration with ferroelectric transistors as memory cells has been proposed in T. Nakamura, Y. Nakao, A. Kamisawa, H. Takasu: A Single Transistor Ferroelectric Memory Cell, IEEE, 1995, pages 68 to 69. Set forth in the document is that each of the ferroelectric transistors is connected between a supply voltage line and a bit line. Selection is effected through a back gate. In such a case, the ferroelectric transistors used have a floating gate electrode between the ferroelectric layer and the gate oxide, the charge of which electrode is controlled by the polarization state of the ferroelectric layer.
It has been shown that in such memory cell configurations, when the information is read, a voltage is also dropped across non-selected memory cells, which voltage can lead to corruption of the information stored in the individual memory cells. Such corruption is attributed to the fact that umklapp or fold-over processes of the domains in ferroelectric materials are of a statistical nature and can be brought about even at low voltages.
It is accordingly an object of the invention to provide a memory cell configuration that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has memory cells each with a ferroelectric transistor in which alteration of the written-in information during the reading operation is avoided.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a memory cell configuration, including a semiconductor substrate having a surface, strip-type doped well regions, and integrated memory cells, each of the memory cells having a ferroelectric transistor, a diode structure, and word lines running substantially parallel to one another. The ferroelectric transistor has a first source/drain region, a second source/drain region, a first gate intermediate layer and a first gate electrode disposed at the surface of the substrate between the first and second source/drain regions, the first gate intermediate layer containing at least one ferroelectric layer, a second gate intermediate layer and a second gate electrode disposed between the first and second source/drain regions in a direction of a connecting line between the first and second source/drain regions, the second gate intermediate layer containing a dielectric layer, and, beside the first gate intermediate layer, the second gate intermediate layer, the first gate electrode, and the second gate electrode connected to one another through the diode structure. The second gate electrode is respectively connected to one of the word lines and the strip-type doped well regions cross the word lines and respectively run in a region between the first and second source/drain regions of the ferroelectric transistor.
With the objects of the invention in view, there is also provided a memory cell configuration where the ferroelectric transistor has a second gate intermediate layer and a second gate electrode disposed between the first and second source/drain regions.
With the objects of the invention in view, there is also provided a memory cell configuration where the ferroelectric transistor has a second gate intermediate layer and a second gate electrode disposed between the first and second source/drain regions substantially along a line connecting the first and second source/drain regions.
In the memory cell configuration, a multiplicity of memory cells, each having a ferroelectric transistor, are provided in an integrated manner in a semiconductor substrate. The respective ferroelectric transistor includes two source/drain regions. Between the source/drain regions a first gate intermediate layer and a first gate electrode are disposed at the surface of the semiconductor substrate, the first gate intermediate layer containing at least one ferroelectric layer, and between which a second gate intermediate layer and a second gate electrode are disposed in the direction of a connecting line between the source/drain regions. Beside the first gate intermediate layer, the second gate intermediate layer containing a dielectric layer, the first gate electrode, and the second gate electrode are connected to one another through a diode structure. Furthermore, word lines that substantially run parallel are provided in the memory cell configuration, the second gate electrode in each case being connected to one of the word lines. Furthermore, strip-type doped well regions are provided in the semiconductor substrate, which well regions cross the word lines and in each case run in the region between the source/drain regions of the ferroelectric transistors.
In the memory cell configuration, one of the memory cells is selected by the associated word line and the associated strip-type doped well region. The non-selected strip-type doped well regions and word lines have applied to them voltage levels such that the polarization state of the ferroelectric layer in the non-selected memory cells is not altered. The provision of the strip-type doped well regions allows the application of an individual substrate voltage to the ferroelectric transistors disposed along the respective strip-type doped well region.
Because, in the ferroelectric transistor, the first gate electrode and the second gate electrode are disposed respectively beside one another along the connecting line between the source/drain regions, the channel region of the ferroelectric transistor is subdivided. One part of the channel region, which is disposed beneath the first gate electrode, can be driven by the charge that is effective on the first gate electrode. Another part of the channel region, which is disposed beneath the second gate electrode, can be driven by the charge that is effective on the second gate electrode. A current can flow between the source/drain regions only when both the part of the channel region below the first gate electrode and the part of the channel region below the second gate electrode are conducting.
The diode structure is connected in a polarity such that when a voltage is present at the second gate electrode that controls the conductivity of the channel region beneath the second gate electrode, the diode structure turns off and the first gate electrode is thereby isolated from the voltage. The configuration ensures that the voltage for driving the second gate electrode is dropped only across the second gate electrode. The first gate electrode is isolated from the voltage by the diode structure, so that no voltage is dropped across the ferroelectric layer in such a case. The configuration prevents alteration of the polarization of the ferroelectric layer and, hence, of the stored information during the reading operation, during which the second gate electrode is driven.
By contrast, for writing and erasing information, a voltage that is suitable for polarizing the ferroelectric layer can be applied to the second gate electrode. In such a case, the information is written by a voltage that is greater than the reverse voltage of the diode structure and that polarizes the ferroelectric layer in one direction. The information is erased by a voltage with a different sign, so that the diode structure is forward-biased and the voltage dropped across the ferroelectric layer polarizes the latter in the other direction.
In the memory cell configuration, the ferroelectric transistor is sufficient per memory cell to store information in a nonvolatile manner and to read out the information nondestructively. An additional selection transistor is not necessary. Therefore, the memory cell configuration can be realized with a reduced space requirement.
In accordance with another feature of the invention, adjacent ferroelectric transistors along a word line are preferably connected up in series in the memory cell configuration. In such a case, the ferroelectric transistor of one of the memory cells is connected respectively between adjacent bit lines between which a current flow through the ferroelectric transistor is evaluated during the reading operation.
With regard to a reduced area requirement, in accordance with a further feature of the invention, it is advantageous in the configuration for the interconnected source/drain regions of adjacent ferroelectric transistors along a word line to be formed as a common diffusion region. In such a case, the width of the strip-type doped well regions, parallel to the course of the word lines, is in each case less than the distance between the centers of the source/drain regions of the respective ferroelectric transistor. The configuration ensures that the strip-type doped well regions of adjacent ferroelectric transistors along a word line are insulated from one another by the doping of the semiconductor substrate and the associated ferroelectric transistors can, thus, be driven unambiguously through the respective strip-type doped well regions.
With regard to reliable insulation between adjacent strip-type doped well regions, in accordance with an added feature of the invention, it is advantageous to provide the width of the strip-type doped well regions to be so large that the two source/drain regions of the respective ferroelectric transistor are disposed within the respective strip-type doped well region. In such a case, it is advantageous for adjacent strip-type doped well regions to be isolated from one another by a dielectric isolation structure that avoids the occurrence of latch-up effects between adjacent strip-type doped well regions.
In accordance with an additional feature of the invention, the second gate intermediate layer and the second gate electrode are preferably each composed of two partial structures that are disposed mirror-symmetrically with respect to the first gate intermediate layer. The two partial structures of the second gate electrode are electrically connected to one another. Such a configuration has the advantage that the voltage present at the second gate electrode brings about, during the reading mode, an electric field such that the ferroelectric layer lies on an equipotential line and, consequently, no alteration whatsoever of the polarization of the ferroelectric layer occurs. This configuration of the invention is particularly insensitive to interference.
In accordance with yet another feature of the invention, it is advantageous to provide a dielectric layer between the surface of the semiconductor substrate and the ferroelectric layer, which dielectric layer facilitates the application of the ferroelectric layer.
In accordance with yet a further feature of the invention, with regard to the fabrication of the ferroelectric transistor, it is advantageous for the dielectric layer that is disposed in the first gate intermediate layer between the semiconductor surface and the ferroelectric layer and the dielectric layer that is part of the second gate intermediate layer to be formed as continuous dielectric layer at whose surface the stack including the ferroelectric layer and the first gate electrode is produced.
Preferably, in accordance with yet an added feature of the invention, the first gate electrode and/or the second gate electrode are/is part of the diode structure. As such, the space requirement of the diode structure decreases.
In accordance with yet an additional feature of the invention, the first gate electrode preferably has polycrystalline silicon doped by a first conductivity type. The second gate electrode likewise has polycrystalline silicon doped by a second conductivity type, which is opposite to the first conductivity type. In such a case, the first gate electrode adjoins the second gate electrode, so that the diode structure is formed by the first gate electrode and the second gate electrode. In the configuration, only four terminals are required for operating the ferroelectric transistor, two on the source/drain regions, one on the second gate electrode, and one for the strip-type doped well region. As an alternative, in the configuration, the first gate electrode and the second gate electrode respectively may be formed from correspondingly doped silicon grown epitaxially.
For technological reasons, in accordance with again another feature of the invention, it may be advantageous to provide between the ferroelectric layer and the first gate electrode an auxiliary layer made, for example, of platinum or of dielectric material, for example, made of CeO2, ZrO2, or the like with a thickness of approximately 2 to 10 nm, which avoids undesirable properties of the ferroelectric layer such as, for example, fatigue or imprint resistance. If the auxiliary layer is formed from conductive material, then it is insulated from the second gate electrode.
It lies within the scope of the invention to use a semiconductor substrate that has monocrystalline silicon at least in the region of the active regions of the ferroelectric transistors. In particular, a monocrystalline silicon wafer or the monocrystalline silicon layer of an SOI substrate is suitable as the semiconductor substrate. Furthermore, all semiconductor substrates that are appropriate for the fabrication of integrated circuits are suitable.
In accordance with a concomitant feature of the invention, the first gate intermediate layer contains at least one of the group consisting of CeO2, ZrO2, Y2O3, and SrTiO3, the second gate intermediate layer contains at least one of the group consisting of SiO2, CeO2, ZrO2, and SrTiO3, the ferroelectric layer contains at least one of the group consisting of strontium bismuth tantalate, lead zirconium titanate, lithium niobate, and barium strontium titanate, and the semiconductor substrate contains monocrystalline silicon.
It also lies within the scope of the invention for the first gate intermediate layer to contain a dielectric layer made of CeO2, ZrO2, Y2O3, or another oxide having the largest possible dielectric susceptibility, such as, for example, SrTiO3. In particular, SiO2, CeO2, ZrO2, Y2O3, or another oxide with the largest possible dielectric susceptibility, such as, for example, SrTiO3, is suitable for the dielectric layer in the second gate intermediate layer. The ferroelectric layer may be made, inter alia, of strontium bismuth tantalate (SBT), lead zirconium titanate (PZT), lithium niobate (LiNbO3), or barium strontium titanate (BST).
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.